1. Field of the Invention
The present invention relates generally to design of analog to digital converters, and more specifically to an interleaved analog to digital converter with improved compensation for parameter mismatch among individual converters.
2. Related Art
An analog to digital converter (ADC) refers to a component, which samples an input signal, and provides (generates) digital codes corresponding to the strength of the analog signal at the sampled time instances. A sampling clock is generally provided as an input to the ADC that determines the time instances.
An interleaved ADC refers to a component which employs multiple ADCs (each referred to as a converter henceforth) typically connected in parallel, with each converter sampling the signal generally at a same rate (or frequency), but offset in time with respect to each other in a cyclical fashion. Thus, for example, assuming equal time offset (a) for sampling, in an arrangement containing three ADCs, the first ADC samples the signal at a time instance t, the second ADC at a time instance t+a, the third ADC at a time instance t+2a, and the cycle repeats again. The samples generated by the converters are provided as the output stream of the interleaved ADC.
As may be readily appreciated, an interleaved ADC effectively provides a higher sampling rate by interleaving the input samples across multiple converters. The implementation of each ADC is also simplified since more time is available to provide the corresponding sample.
It is generally desirable that all the converters of an interleaved ADC have identical performance parameters (parameter values) since it would ensure that the stream of generated digital codes would accurately represent the shape of the input signal. A mismatch is said to have occurred if parameters are not identical among the converters.
One type of parameter mismatch is gain mismatch. A gain mismatch is present when all converters contained in an interleaved ADC do not each have the same gain in the amplifier stage. In general, amplifiers with higher gains would generate higher values of digital codes, for the same strength of the sampled input signal.
Another type of parameter mismatch is DC offset mismatch. ADC offset mismatch is present when all converters in the interleaved ADC do not each have the same DC offset error, which may be measured as the digital code generated when the input signal has a strength (voltage) of zero volts. For example, a higher DC offset would imply higher values to be generated assuming positive DC offset.
Yet another type of parameter mismatch is sampling time mismatch due to sampling time (timing) errors. A sampling time mismatch is present when sampling time instances of the individual converters are not all separated in time by equal amounts. As noted above, in an ideal interleaved ADC, the sampling instances of individual converters need to occur at time intervals separated equally in time.
Accordingly, there have been several prior attempts to compensate for parameter mismatches.
In one prior approach, the interleaved ADC is placed in a calibration mode, and the individual converters are fed with a test signal to estimate the mismatch parameters. This approach requires additional hardware for generating the test signal and also requires a calibration phase during which the ADC cannot be used for data conversion. Further, this approach does not allow for tracking parameter mismatch variations (e.g., due to temperature), which might occur during operation over an extended period of time.
The present invention provides a method and apparatus for compensating for parameter mismatch among individual converters in an interleaved ADC, and overcomes at least some of the drawbacks associated with prior approaches.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.